1. Field of the Invention
This invention relates to computer systems and more particularly to parallel port circuitry employed within computer systems.
2. Description of the Relevant Art
Parallel ports are widely employed within computer systems to allow a convenient and fast mechanism to transfer data to external peripheral devices such as printers. A parallel port typically includes a data latch which is written with data in response to a write cycle executed by the processor to a predetermined address location. Once this data has been stored within the latch of the parallel port, a control circuit associated with the parallel port causes the data to be transferred to the external peripheral device. The external peripheral device acknowledges receipt of the data and the control circuit responsively returns a ready signal to the processor to release it from the current write cycle.
Parallel ports may further be used to receive data from an external peripheral device. For this situation, the external peripheral typically asserts a parallel port interrupt to the microprocessor to indicate that it is ready to transfer data. The microprocessor responsively executes a read cycle to the parallel port, and the peripheral device asserts an acknowledge signal to indicate that valid data is currently being provided to the parallel port.
Unrecoverable failures may occur within current implementations of parallel port mechanisms if the communication link to the external device is severed or if the communications fail. If the processor executes a write or read cycle to the parallel port and an acknowledge signal is not returned by the peripheral device indicating that it has accepted the write data or that it has provided the read data, the computer system will "hang". In other words, the computer system will wait indefinitely for the peripheral device to provide an acknowledge signal. Once such a situation arises, the computer system must typically be reset or restarted to release the processor.